The present invention relates to a manufacturing method os a semiconductor device, and more specifically concerns a polishing process and a dicing process of a semiconductor wafer.
[Prior Art Example 1]
Referring to FIG. 11 and FIGS. 12(a) to FIG. 12(g), the following description will discuss processes from the rear-face polishing process to the dicing process of a semiconductor wafer disclosed in Japanese Laid-Open Patent Application No. 22358/1995 (Tokukaihei 7-22358, published on Jan. 24, 1995).
Before a rear-face polishing process, a semiconductor wafer 101 is subjected to an electrical test by means of probing (hereinafter referred to as xe2x80x9cwafer testxe2x80x9d) (S101, see FIG. 12(a)) and a protection and reinforcing tape 102 is affixed onto the front face (element formation face) thereof (see S102, FIG. 12(b)). The protection and reinforcing tape 102 is formed by, for example, laminating an acrylic bonding agent onto a polyethylene terephthalate (PET) film.
After polishing the rear face of the semiconductor wafer 101 (S103, FIG. 12(c)), the rear face of the semiconductor wafer 103 is affixed onto a dicing tape 106 through a carrier frame 105 with the protection and reinforcing tape 102 being affixed on the front face thereof (S104, FIG. 12(d)).
Next, the protection and reinforcing tape 102 is separated from the front face of the semiconductor wafer 103 (S105, FIG. 12(e)). In this case, as illustrated in FIG. 12(e), a separation tape 104, which has a greater adhesive force than the adhesive force between the protection and reinforcing tape 102 and the semiconductor wafer 103, is used so as to separate the protection and reinforcing tape 102.
Successively, after washing residual bonding agent from the front face of the semiconductor wafer 103 by means of ultrasonic washing with pure water (S106, FIG. 12(f)), the semiconductor wafer 103 is full-cut or semi-full-cut through a dicing process using a diamond wheel so that a semiconductor chip 107 having a predetermined size is formed (S107, FIG. 12(g)).
Next, the sequence proceeds to a die bonding process. In the die bonding process, only one of the semiconductor chips 107 is pushed up by a pin from the rear face of the semiconductor wafer 103 through the dicing tape 106 so that this is subjected to a die bonding process by using the die bonding collet 103 (S108). Here, those semiconductor wafers 103 that have been subjected to the semi-full dicing process undergo the die bonding process after a breaking process.
In the following Prior Art Examples 2 through 4, an explanation will be given of methods for carrying out chemical etching on the polished rear face and dicing cut face of the semiconductor wafer.
[Prior Art Example 2]
Referring to FIG. 13, an explanation will be given of a method for chemically etching the rear polished face of the semiconductor wafer disclosed in Japanese Laid-Open Patent Application No. 201805/1995 (Tokukaihei 7-201805 (published on Aug. 4, 1995).
The front face (element formation face) of the semiconductor wafer 103 having the polished rear face is covered with a protection film 108 (for example, a rubber tape, etc.), and this is attached to a securing base 109 that is freely rotated by a rotation axis 110, with the rear face of the semiconductor wafer 103 facing up. While the wafer securing base 109 is being rotated at a high speed, etchant (for example, a hydrogen fluoride etchant in the case of a semiconductor 103 of Si series) is discharged from an etchant spouting nozzle 111 onto the rear face of the semiconductor wafer 103 that faces up, and at the same time, a cooling fluid (for example, pure water or nitrogen gas), which is inert to the etching reaction, is discharged through a cooling fluid spouting nozzle 112 onto the front face of the semiconductor wafer 103 that faces down; thus, the chemical etching process for eliminating stress resulting from polishing is carried out.
[Prior Art Example 3]
Referring to FIGS. 14(a) through 14(d), an explanation will be given of a method for chemically etching the dicing cut face disclosed in Japanese Laid-Open Patent Application No. 161665/1995 (Tokukaihei 7-161665, published Jun. 23, 1995).
First, a novolak resin is dropped onto the front face of a semiconductor wafer 103 and this is rotated so as to form a protective film 113 (FIG. 14(a)). Next, a dicing sheet (dicing tape 106) is affixed to the front face (element formation face) of the semiconductor wafer 103, and a dicing process is carried out by using a blade so as to divide it into semiconductor chips 107 (FIG. 14(b)). The semiconductor chips 107 thus cut off are immersed into an etchant 114 of a sulfuric-acid type, an ammonia type, etc. so that a machining-affected layer on the cut face 107a is removed (FIG. 14(c)). Thereafter, the semiconductor chips 107 are immersed and washed in a solvent 115 such as acetone so that the protective layer 113 formed on the front face of the semiconductor chip 107 is removed (FIG. 14(c)).
[Prior Art Example 4]
Referring to FIG. 15 and FIG. 16(a) to FIG. 16(f), an explanation will be given of a method for carrying out a rear-face polishing process by chemical etching after a dicing process, which is disclosed in Japanese Laid-Open Patent Application No. 117445/1988 (Tokukaishou 63-117445, published May 21, 1988).
After completion of an IC formation process (S111, FIG. 16(a)), a bump 116 is formed by means of electrolytic plating through a bumping process on each IC of the semiconductor wafer 101 prior to polishing (S112, FIG. 16(b)). Next, a groove having a predetermined depth is formed along ICs from the front face (element formation face) by a dicing process (S113, FIG. 16(c)). Successively, after a wax applying process in which the front face of the semiconductor wafer 101 is coated with wax 117 having chemical etching resistance (S114, FIG. 16(d)), the semiconductor wafer 101 is immersed in a chemical etchant 118 in an etching process so that the rear face thereof is etched so as to have a predetermined thickness (S115, FIG. 16(e)). Then, the semiconductor wafer 103 is washed by water so as to wash the chemical etchant 118 away, and the wax 117 is removed by a solvent. Thereafter, the semiconductor wafer 103 is subjected to a breaking process so as to separate it into semiconductor chips 107 (S116, FIG. 16(f)).
[Prior Art Example 5]
Referring to FIG. 17(a) to FIG. 17(e), an explanation will be given of a manufacturing method for semiconductor chins disclosed in Japanese Examined Patent Publication No. 2737859/1998 (published on Jan. 16, 1998).
First, a semiconductor wafer 101 having a wafer surface pattern formed thereon is checked to see its characteristics (FIG. 17(a)). Then, the wafer 101 is subjected to a semi-full dicing process so as to form the shape of individual chips thereon with a portion x corresponding to approximately half the thickness left from the wafer element formation face (FIG. 17(b)). Thereafter, stains and water adhering to the wafer 101 are removed. Next, a base film 122 is affixed thereon with a bonding agent 121 so as to secure the chips during a rear-face polishing process on the next step (FIG. 17(c)). Moreover, a fixing jig 123 is placed on the periphery of the wafer 101. Then, the wafer 101 is polished from the rear face side up to a predetermined amount so as to separate it into individual chips 107 (FIG. 17(d)). Thereafter, stains and water adhering to the wafer 101 are removed.
Next, the chips 107, bonded to the base film 122, are pushed from the base film 122 side by a pushing jig 124 so that they are allowed to adhere to a joining material 126 that adheres to a die pad 125 shifting in the arrow direction; thus, the chips 107 are separated from the base film 122 by using the adhesive strength of the joining material 126, with the result that the chips 107 are transported while being bonded to the die pad 125 (FIG. 17(e)).
In the methods shown in the Prior Art Examples 1 and 2, it has been generally known that since a machining-affected layer appears on the rear face at the time of polishing the semiconductor wafer 101, a stress is exerted, resulting in problems in the semiconductor wafer 103 after having been subjected to rear-face polishing.
This phenomenon becomes more conspicuous as the semiconductor wafer 101 is made thinner (for example, not more than 200 xcexcm in the case of a chip card), and deflection, exerted in the semiconductor wafer 103 after polishing the rear face, becomes greater. The resulting problem is that since it becomes difficult to transport or secure the semiconductor wafer 103, it might be easily broken. Here, in order to miniaturize semiconductor devices in which semiconductor chips 107 are assembled, there are demands for reducing the thickness of a semiconductor wafer 103 to not more than 200 xcexcm.
In this respect, in Prior Art Example 1, after the polishing process of the semiconductor wafer 101, until having been divided into individual pieces of semiconductor chips 107 through the dicing process, since the semiconductor wafer 103 is reinforced by either the protection and reinforcing tape 102 or the dicing tape 106, it is possible to reduce the possibility of the semiconductor wafer 103 being damaged during the handling and transportation process.
However, in the dicing process thereafter, since cracks might occur in the cut face 107a, the strength per unit area of the semiconductor chip 107 decreases. Moreover, in the case of the thickness of the semiconductor wafer 103 not more than 200 xcexcm, chipping (cracks not bridging from the front face to the rear face) and cracks (those bridging from the front face to the rear face) tend to occur in the rear face of the semiconductor wafer 103 during the dicing process, and in the case of the semi-full dicing, chipping to the rear face and cracks occur at the time of breaking, resulting in the possibility that the wafer might be easily damaged in the following processes.
Moreover, in Prior Art Example 2, defective areas having a machining affected layer and fine cracks that occur at the time of rear-face polishing are removed by chemical etching. However, the problems of fine cracks in the cut face, a machining-affected layer, chipping and cracking at the time of the dicing process thereafter still remain in the same manner as Prior Art Example 1.
Furthermore, in Prior Art Example 3, defective areas having a machining-affected layer and fine cracks that occur at the time of dicing are removed by chemical etching. However, since the processes after the dicing are carried out for each piece of the semiconductor chip 107, problems arise with working efficiency at the time of mass production. Here, even if Prior Art Example 2 and Prior Art Example 3 are combined, problems still arise with working efficiency since the processes after the dicing are carried out for each piece of the semiconductor chip 107.
Moreover, in the above-mentioned Prior Art Example 4, chipping and cracks tend to occur due to breaking after washing, and since the cut face 107a, subjected to the semi-full dicing, is coated with wax 117, it is not possible to carry out chemical etching on the cut face 107a after the dicing process, resulting in problems of fine cracks in the cut face, a machining-affected layer and chipping and cracking. In addition, in Prior Art Example 4, a removing process for wax 117 is required, and the process after removal of the wax 117 has to be carried out on each piece of the semiconductor chips 107; therefore, a problem arises with working efficiency.
Furthermore, in the above-mentioned Prior Art Example 5, since damaged areas such as a machining-affected layer and fine cracks resulted from the dicing process and the rear-face polishing process are not removed, chip cracks and chipping or chip deflection due to an unwanted stress tend to occur, resulting in damages to the semiconductor wafer in the following steps.
The objective of the present invention is to provide a manufacturing method for a semiconductor device which can carry out a polishing process and a dicing process safely without damaging the semiconductor wafer, without causing cracks, and without chipping.
In order to achieve the above-mentioned objective, the manufacturing method for a semiconductor device of the present invention comprises the steps of:
semi-full dicing a semiconductor wafer so as to leave a dicing residual portion with a predetermined thickness between devices on the semiconductor wafer;
forming a protective layer (film) having a chemical etching resistant property on the element formation face of the semiconductor wafer;
chemically etching the semiconductor wafer having the protective layer formed on the element formation face from the rear face side so as to polish the rear face of the semiconductor wafer, so as to remove the dicing residual portion to divide the semiconductor wafer into individual semiconductor chips, and so as to remove defective areas occurring in the cut face of the semiconductor wafer due to the semi-full dicing process.
With the above-mentioned method, the chemical etching makes it possible to simultaneously carry out the rear-face polishing process of the semiconductor wafer, the dividing process to each piece of the semiconductor chips and the removing process of defective areas such as, a machining-affected layer and chipping and cracking in the cut face of the semiconductor chip due to the semi-full dicing process.
Therefore, it is possible to eliminate the breaking process after the semi-full dicing process that has been conventially required, to reduce the number of processes, and also to prevent cracks and chips that used to occur at the time of breaking. Thus, it becomes possible to carry out a polishing process and a dicing process safely without damaging the semiconductor wafer, without causing cracks and chips.
Moreover, in order to achieve the above-mentioned objective, the manufacturing method for a semiconductor device of the present invention is arranged so that in the above-mentioned semi-full dicing process, the semiconductor wafer is subjected to semi-full dicing from the element formation face so as to leave a dicing residual portion with a predetermined thickness on the rear face side that is the face opposite to the element formation face of the semiconductor wafer, and then, in the above-mentioned protective layer forming process, a protective layer having a chemical etching resistant property is formed on the element formation face of the semiconductor wafer.
With the above-mentioned method, after the semi-full dicing process from the element formation face (front face), the semiconductor wafer having the protective layer formed on the element formation face is subjected to a chemical etching process with the element formation face being protected by the protective layer, so as to simultaneously carry out the rear-face polishing process of the semiconductor wafer, the dividing process to each piece of the semiconductor chips and the removing process of defective areas such as, a machining-affected layer and cracks and chips in the cut face of the semiconductor chip due to the semi-full dicing process.
In other words, in the chemical etching process of the above-mentioned method, first, the semiconductor wafer is etched in the thickness direction of the semiconductor chip from the rear face. In this case, since the dicing residual portion is also simultaneously etched from the rear face, when the etching has reached the thickness (dicing left amount) of the dicing residual portion, the semiconductor wafer is separated into individual pieces of semiconductor chips. After the separation to the semiconductor chips, etchant enters a groove between the adjacent semiconductor chips formed in the semi-full dicing process so that each of the semiconductor chips is subjected to etching also in the width direction from the cut face; thus, it becomes possible to remove the defective areas caused by the semi-full dicing process.
Moreover, in order to achieve the above-mentioned objective, the manufacturing method for a semiconductor device of the present invention is arranged so that, after forming the protective layer having dicing protective and chemical etching resistant properties on the element formation face of the semiconductor wafer in the above-mentioned protective layer forming process, the semiconductor wafer is subjected to semi-full dicing from the rear face that is the face opposite to the element formation face so as to leave a dicing residual portion with a predetermined thickness on the element formation face of the semiconductor wafer in the semi-full dicing process.
In the above-mentioned method, after forming the protective layer on the element formation face, the semiconductor wafer, after having undergone the semi-full dicing from the rear face, is subjected to a chemical etching process with the element formation face being protected by the protective layer, so as to simultaneously carry out the rear-face polishing process of the semiconductor wafer, the dividing process to each piece of the semiconductor chips and the removing process of defective areas such as, a machining-affected layer and cracks and chips in the cut face of the semiconductor chip due to the semi-full dicing process.
In other words, in the chemical etching process of the above-mentioned method, first, the semiconductor wafer is etched in the thickness direction of the semiconductor chip from the rear face. Simultaneously with this process, since etchant enters a groove between the adjacent semiconductor chips formed in the semi-full dicing process, the dicing residual portion is etched from the rear face side, with the result that when the etching has progressed to the dicing residual amount and reached the element formation face of the semiconductor wafer, the semiconductor wafer is divided into semiconductor chips. Moreover, simultaneously with this process, each of the semiconductor chips is subjected to etching also in the width direction from the cut face; thus, it becomes possible to remove the defective areas caused by the semi-full dicing process.
In addition, in the above-mentioned method, the semi-full dicing process is carried out from the rear face, it is possible to eliminate an exchanging process for the dicing protective tapes on the semiconductor wafer, to reduce the number of processes, and consequently to prevent damages, etc., to the semiconductor element due to mishandling, etc. during shifting processes between processes.